D4.1 Pilot Modular Architecture Description

The goal of the EUPEX Pilot is to integrate the different hardware components (provided by WP4) and software components (provided by WP5) into a single pilot system as to show the interoperability and the maturity of these components for future HPC systems, targeting exascale-size machines. This deliverable D4.1 depicts the suggested architecture for the EUPEX Pilot, focusing on the hardware components: its compute nodes, the interconnect and the memory and storage related aspects.

The definition of the compute nodes themselves is _not_ in the scope of this deliverable: the design criteria and choices for the GPU and the CPU blade are detailed in D4.2. Some parameters of this architecture have already been defined during the proposals phase, and others depend on SiPearl Rhea chip and cannot be influenced neither. For the remaining parameters, input from WP3 and WP5 was collected in a co-design approach.

This deliverable describes the structured dialogue with WP3 for understanding their requirements. It details the different parameters we examined and the suggested architecture for the pilot. The elements of this deliverable will feed into D6.2, which is due on M24 and will refine – if need be – the pilot architecture and define the annex components of the pilot system.